library ieee;
use ieee.std_logic_1164.all;

--输入一个clk（5000Hz），输出1Hz信号
entity divider is
  port  (clk:in std_logic;
             clk1Hz: out std_logic );
end;

architecture art of divider is

signal clk2Hz : std_logic ;

begin
p1: process (clk)
      variable count1 : integer range 0 to 2500;
         begin
            --clk每2500次（0.5s）clk2Hz多一个上升沿（毛刺）
             if clk'event and clk='1' then
                 if count1 = 2499 then 
                    count1 := 0;
                    clk2Hz <='1';
                 else count1 :=count1+1;
                    clk2Hz<='0';
                 End if;
             End if;
   end process;

p2: process ( clk2Hz )
   --初值赋值形式：variable count2 : std_logic :='1';
     variable count2 : std_logic ;
    begin
       if clk2Hz'event and clk2Hz='1' then
            count2 := not count2; 
       if count2 = '1'then
            clk1Hz <='1';--产生真正的1Hz信号
       else 
            clk1Hz <='0';
       end if;
       end if;
       
    end process;              
end art;
